Heed the warning and it will save you days in debugging with random error appearances that simply won’t go away with any numbers of repairs and recompilations because you’re simply not recompiling your circuitry!

On designing FPGAs or CPLDs on Altera with their primary software designer, the Quartus, a compilation of a multi-level circuit will result in the compilation of only the topmost level. In order a change in say the bottom level, you would have to compile the bottom level, create new module symbol, go to the next level, update the symbol, compile that level, create module symbol and move one level up until the top which obviously makes it extremely ridiculous to debug.

Here’s some sample code for VHDL that does the same thing as block diagrams:

Suppose you have pre-made level2 that you wish to put together

architecture structure of toplevel is
    component level2
        port (a,b: in bit;
        c: out bit);
    end component;
begin
    c1: level2
        port map (in11,in12,out1);
    c2: level2
        port map (int21,in22,out2);
end structure;